Please do all of the parts.

Consider a direct-mapped cache with 4 word blocks, which is byte addressable. a) If this cache holds 64 KB of data, how many index bits does it need and why? b) What is the total cache size that holds these data considering that it uses 2-bit word offset and 2-bit block offset (do not forget about the Valid bits it uses); c) d) We decide to increase the amount of data the cache can hold to 128 KB. Each block this e) What is the total size of this new cache, if it uses 3-bit word offset and a number of bits f) Draw the cache in question d) and compare the number of index and tag bits with those Sketch this direct-mapped cache, and explain how hits and misses are determined. time has 8 words. How many index bits does this new cache have and why? needed by the MUX to determine which word is needed by the pipeline of question c)