make sure to use a 16 bit carry adder
As an exercise in a simple design you are required to do the following: 1. Use the fulladder Verilog program as given in Laboratory exercise 1 and write another short Verilog program to implement an 16-bit ripple carry adder. Write your own test bench to illustrate that your 16-bit ripple carry adder functions correctly. Use the wave program to illustrate sample results. 2. Use the 4-bit carry lookahead adder Verilog program in Laboratory exercise 1 and write another short Verilog to implement a two-level 16-bit carry lookahead adder as described in the lectures on carry lookahead adder. Write your own test bench to illustrate that your 16-bit carry lookahead adder functions correctly. Use the wave program to illustrate sample results. The report shall include the following: 1. Introduction to Laboratory Exercise 1 with the objective of designing a ripple carry adder including also the carry lookahead adder and verifying the behavioral and functional performance using ModelsimAltera simulation tool through a test bench. 2. A brief explanation of your Verilog programs describing the adder circuits i.e., a 16-bit ripple carry adder, and a 16-bit carry lookahead adder. For this parpose, you are required to compare the operation of the nwo different adders in terms of logic and time delays. 3. A discussion on the interpretation of the results obtained for each of the 2 different circuits in the form of illustrations of the waveforms with annotated figures as per the description in the laboratory manuals. A screenshot copy of the results is considered incomplete without any accompanying interpretation and explanation on the meaning of the Mllustration. Marks will only be given for a clear explanation of the illustrations. 4. A statement on the lesson learned in using Quartus as an EDA tool and the purpose of designing using Verilog (including features of the Verilog language) and the IP Cores and simulating the circuit using Modelsim simulator 5. This report is worth 10% of the overall assessment for the course. Marks will be given for concise and clear explanation of the work done. Introduction to Verilog and Quartus Prime Software The purpose of this laboratory are: 1. To give an introduction to Altera Quartus Prime software for the purpose of learning Verilog as a programming tool for digital circuit design. 2. To develop programs in Verilog language for designing computer system circuits and verifying the behavioral and functional performance using Modelsim-Altera simulation tool. References: 1. Stephen Brown and Zvonko Vranesic: Fundamentals of Digital Logic with Verilog Design, 3rd Edition. 2. Altera Quartus Prime Introduction - Using Verilog Designs, Tutorial Using Quartus Prime CAD Software, May 2013 Verilog is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as fieldprogrammable gate arrays and integrated circuits. Altera Quartus Prime is a Computer Aided Design (CAD) software that makes it easy to implement a desired logic circuit by using a programmable logic device, such as a field-programmable gate array (FPGA) chip. A typical FPGA CAD flow is illustrated in Figure 1. The CAD flow involves the following steps
