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1.10 (24 pts) We have begun fabrication of a 300cm wafer, designed to produce big System-on-Chip dies, 20mm x 20mm. a. What's the size of the area of each wafer: cm? b. How many whole and fractional SoC dies can you fit? dies Round down to the nearest multiple of 10 to remove the partial dies at the circular edge: dies c. (5 pts) If you have a defect rate of 1 defect per cm, how many defects would you on average find across the surface of a wafer? d. How many perfect 20 mm x 20 mm dies are you likely to produce per wafer? e. If you could reduce the number of defects per die to say, 50, how many of your dies would you expect to be free of defects? f. If yield is the % of good dies versus total dies you produce, what's our yield? According to Adam Traidman from Chip Estimate, the average die sizes being produced look like this these days: Smallest die size: 0.683 mm x 0.683 mm at the 90 nm technology node 1.533 mm x 1.533 mm at the 65 nm technology node Average die size 7.020 mm x 7.020 mm at the 90 nm technology node 2.130 mm x 2.130 mm at the 65 nm technology node Biggest die size: 20.253 mm x 20.253 mm at the 65 nm technology node g. So our 20mm x 20mm die is a big one. What if we switched to using our 300mm wafers to make small dies, say 1mm x 1mm. Rounding down to the nearest 1000, how many dies would we be able to fabricate on our wafers? h. If we build small dies, with that same 50 defects spread across your wafer, what would our yield be now? If you want an 80% yield for your large dies (20mm x 20mm), you need to reduce the defect rate. How many of your dies from (b) can be defective to keep you at 80%? j. If that's the number of defects across your wafer, about how many per cm is that? k. If you think you'll be able to sell 4M of these dies, how many wafers will you have to produce? Round up to the next 100. 1. Your product manager is told by finance that you have to generate $800M to pay for the factory retooling your share of R&D, and the desired profit, how much will you sell each die for? 1.10 (24 pts) We have begun fabrication of a 300cm wafer, designed to produce big System-on-Chip dies, 20mm x 20mm. a. What's the size of the area of each wafer: cm? b. How many whole and fractional SoC dies can you fit? dies Round down to the nearest multiple of 10 to remove the partial dies at the circular edge: dies c. (5 pts) If you have a defect rate of 1 defect per cm, how many defects would you on average find across the surface of a wafer? d. How many perfect 20 mm x 20 mm dies are you likely to produce per wafer? e. If you could reduce the number of defects per die to say, 50, how many of your dies would you expect to be free of defects? f. If yield is the % of good dies versus total dies you produce, what's our yield? According to Adam Traidman from Chip Estimate, the average die sizes being produced look like this these days: Smallest die size: 0.683 mm x 0.683 mm at the 90 nm technology node 1.533 mm x 1.533 mm at the 65 nm technology node Average die size 7.020 mm x 7.020 mm at the 90 nm technology node 2.130 mm x 2.130 mm at the 65 nm technology node Biggest die size: 20.253 mm x 20.253 mm at the 65 nm technology node g. So our 20mm x 20mm die is a big one. What if we switched to using our 300mm wafers to make small dies, say 1mm x 1mm. Rounding down to the nearest 1000, how many dies would we be able to fabricate on our wafers? h. If we build small dies, with that same 50 defects spread across your wafer, what would our yield be now? If you want an 80% yield for your large dies (20mm x 20mm), you need to reduce the defect rate. How many of your dies from (b) can be defective to keep you at 80%? j. If that's the number of defects across your wafer, about how many per cm is that? k. If you think you'll be able to sell 4M of these dies, how many wafers will you have to produce? Round up to the next 100. 1. Your product manager is told by finance that you have to generate $800M to pay for the factory retooling your share of R&D, and the desired profit, how much will you sell each die for