please explain each step
Instruction Format Design for a modifiea MIPS-Lite ISA (Instruction Set Architecture) Design the instruction forma o a version of the MIPS-Lite instruction set assuming we have a l6-bit word. The instructons that should be supported ane Rivne: add. sub. and, or, nor, xor, slt 7 Riype) Immediate: addi. andi. ori. xori. Iw, sw. lb. Ibu, sh. lui. beqz, bnez.sli 13 Immed) . Jumps J. Jal (2 Jump) (3 Rtype or Immediate sll. srl. jr Note: beyz and bnez have the follow ing forat: e Thee are reies Memory is bye ldsabi- Our design objectives are to: S. label SI is equal to zero branch to label. Have all instructions be one word wide Have a fixed format design (avoid sequential decode). Have as long an immediate as possible for load and store effective address calculations (hase register + immediate offset). Have as long amediate as possible forrve branch addressing (PC +immediate offset). .Be able to o a 6-bit immediaie elficiently this requires an S-hit imediate field and an lui instruction) Support hft and jump register instructions in whichever format has more unused opcode or func values (perhaps not R-type Hint: you do not have to have the same number or type of formats as the MIPS. You do not have to have the same size immediate for different formats Be creative wit our designs! Alter you have designed your instruction formats answer the following questions. a. List your instruction formats. Label the different fields of each format and show how n many bits per field and the location of each field within the instruction word. h. What is the ranges of an unsigned immediate? c. What is the rangets) of a signed immediate? d. What is the range of a conditional branch relative to the next PC (in bytes)? e. Sho the jump address calculation f. What is lhe address offset for memory instructions (lw and sw)? Instruction Format Design for a modifiea MIPS-Lite ISA (Instruction Set Architecture) Design the instruction forma o a version of the MIPS-Lite instruction set assuming we have a l6-bit word. The instructons that should be supported ane Rivne: add. sub. and, or, nor, xor, slt 7 Riype) Immediate: addi. andi. ori. xori. Iw, sw. lb. Ibu, sh. lui. beqz, bnez.sli 13 Immed) . Jumps J. Jal (2 Jump) (3 Rtype or Immediate sll. srl. jr Note: beyz and bnez have the follow ing forat: e Thee are reies Memory is bye ldsabi- Our design objectives are to: S. label SI is equal to zero branch to label. Have all instructions be one word wide Have a fixed format design (avoid sequential decode). Have as long an immediate as possible for load and store effective address calculations (hase register + immediate offset). Have as long amediate as possible forrve branch addressing (PC +immediate offset). .Be able to o a 6-bit immediaie elficiently this requires an S-hit imediate field and an lui instruction) Support hft and jump register instructions in whichever format has more unused opcode or func values (perhaps not R-type Hint: you do not have to have the same number or type of formats as the MIPS. You do not have to have the same size immediate for different formats Be creative wit our designs! Alter you have designed your instruction formats answer the following questions. a. List your instruction formats. Label the different fields of each format and show how n many bits per field and the location of each field within the instruction word. h. What is the ranges of an unsigned immediate? c. What is the rangets) of a signed immediate? d. What is the range of a conditional branch relative to the next PC (in bytes)? e. Sho the jump address calculation f. What is lhe address offset for memory instructions (lw and sw)
