Please Generate VHDL code for this circuit:

Q+1 Q1 CK ROM 16 Words X 4 Bits Q+2 CK Q+3 CK Clock Realization of MEALY Sequential Network for BCD to Excess 3 with a ROM Q+1 Q1 CK ROM 16 Words X 4 Bits Q+2 CK Q+3 CK Clock Realization of MEALY Sequential Network for BCD to Excess 3 with a ROM