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5. Design a Finite State machine that will control a 16 word FIFO Data path: You are to design the Controller FSM that will control the Data Path for a 16-word FIFO organized a as a circular buffer. 1. This Data path uses two(2) four-bit counters whose outputs are each decoded by a corresponding 4:16 decoder and compared to each other by a 4-bit to 4-bit comparator, as a shown in the Data Path Diagram shown below. 2. The Wire Counter (WCntr) decoder output always points to or selects) the FIFO word that is going to be written during the next write into the FIFO input (in effect points to one location behind the location that is tail to the queue). Assume this counter is an incrementing counter with wrap-up from 15 to 0. Your state machine should take this into consideration when ordering the counter to increment after a write operation. After a write increment, if the new value of the counter is the same as that of the Read Counter your state machine should move to a state that indicates that the FIFO queue is FULL and no more Write operations can be satisfied until the Read Counter is incremented after a Read operation. 3. The Read Counter (RCntr) decoder output is used to select which FIFO word is at the head of the queue and is going to be output from the FIFO during the next read operation. Assume this counter is an incrementing counter with wrap-up after a valid read operation from 15 to 0. Your state machine should take this into consideration when ordering the counter to increment after read operation. After a read increment, if the new value of the counter is the same as that of the Write Counter your state machine should move to a state that indicates that the FIFO queue is EMPTY and no more Read operations can be satisfied until the Write counter is incremented. 4. Thus when both counters are equal the FIFO could be FULL or EMPTY depending on what was the last operation that took place. This condition is indicated by the Comparator (EO_H) output being asserted. 5. The Write Counter and Read Counter start both at the same value (could be zero or any value) meaning that the FIFO queue is EMPTY 6. Your FIFO Controller FSM should wait for RESET signal and go to the EMPTY state, from there it should go to other states that you will have to determine as part of your solution b. Draw the FIFO Controller FSM Block Diagram