PLEASE I NEED THE TRUTH TABLE AND VHDL CODE FOR THE GIVEN QUESTION

Generator "running 0 " on the D-flip-flops

Similarly to the shift register in Figure 1, but the output Q4 is connected to the input data of the first discharge (DATA). The first trigger sets to "0" when reset=0 , and all another triggers sets to "1".

4 bit

structural

below is the example of the shift register. please help

7.2.3 The example of the shift register Let's consider a synchronous shift register based on the D-triggers, which implements the operation of the logical shift to the right. For example, 1100(12) (piln (a) Crhamn thin marintar in ahawm in Fir 71 Figure 7.1 - Shitt register based on D- tlip-tlops