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V. In this questions the addresses are presented in 32 bit format: however, our machine is 64 bit. Assume 32-bit zero has been removed from the left hand side of these hex numbers. You have a data cache with a hit time of one clock cycle. The hit rate is 90% and the miss penalty is 100 ns to access the next level of the memory hierarchy. Assuming a clock rate of 2 GHz, what is the average memory access time in terms of the number of clock cycles? In the our ARMv8 processor, assuming a direct-mapped cache with 16 2-word blocks that is initially empty, label each reference in the list as a hit or a miss and show the final contents of the cache. The memory is byte-addressable and the addresses below are the address used in a sequence of LDUR instructions ff00f700, Off00f60, Ofe0012c, 0ff00fcc, Ofe0012c, Ofe001e8, 0f000f64, 0f000144, ff00f700, 0f000144, 0f000f64, 0f000180, ff00f700, 0f000f64 In your ARM machine, you are given a 4-way set associative cache with 2-word blocks. The memory is byte-addressable. The cache's total data capacity is 32 words. (i) Calculate the sizes (number of bits) of the fields tag and index (ii) Calculate the total size (in bytes) of the cache. (ii) Assume that the cache is initially empty, and that it uses an LRU replacement policy. Given the following memory accesses in sequence, label whether they will as well. be hits or misses. Calculate the hit rate 0ff00f70, 0ff00f60, Ofe0012c, 0ff00f5c, Ofe0012c, Ofe001e8, 0f000f64, 0f000144, 0fe00204, 0ff00f74, 0f000f64, 0f000128, ff000f70, 0f000f64 (iv) Same as (ii), but the cache is fully associative