please provide a code solutiontionwhy does my simulation have errors module outputter$($

input $[3$:$0]$ state,

input $[15$:$0]$ instruction,

output reg $[10$:$0]$ Rin,

output reg $[10$:$0]$ Rout,

output reg $[1$:$0]$ addSub

$)$;

reg $[3$:$0]$ triReg, RegEnable;

$//$ Internal wires for one$-$hot encoding

wire $[10$:$0]$ triStateWires, enableWires;

$//$ Instantiate oneHot modules

oneHot writeDemux$(.$select$($RegEnable$),.$out$($triStateWires$))$;

oneHot readDemux$(.$select$($triReg$),.$out$($enableWires$))$;

$//$ State machine to control Rin, Rout, and addSub

always @$($state or instruction$)$ begin

triReg $=4\text{'}$b$0000$; $//$ Default no output enable

RegEnable $=4\text{'}$b$0000$; $//$ Default no register enable

addSub $=2\text{'}$b$00$; $//$ Default add operation

case$($state$)$

$4\text{'}$b$0001$: begin $//$ Load

triReg $=4\text{'}$b$1010$; $//$ Data triReg enable

RegEnable $=$ instruction$[11$:$8]$; $//$ Rxin enable

end

$4\text{'}$b$0010$: begin $//$ Move

triReg $=$ instruction$[7$:$4]$; $//$ Rxout

RegEnable $=$ instruction$[11$:$8]$; $//$ Ryin

end

$4\text{'}$b$0011$: begin $//$ Add$/$Sub$/$Xor first state

triReg $=$ instruction$[11$:$8]$; $//$ Rxout

RegEnable $=4\text{'}$b$1000$; $//$ Ain

end

$4\text{'}$b$0100$: begin $//$ Add middle state

triReg $=$ instruction$[7$:$4]$; $//$ Ryout

RegEnable $=4\text{'}$b$1001$; $//$ Gin

addSub $=2\text{'}$b$00$; $//$ add

end

$4\text{'}$b$0110$: begin $//$ Sub middle state

triReg $=$ instruction$[7$:$4]$; $//$ Ryout

RegEnable $=4\text{'}$b$1001$; $//$ Gin

addSub $=2\text{'}$b$01$; $//$ sub

end

$4\text{'}$b$0111$: begin $//$ Xor middle state

triReg $=$ instruction$[7$:$4]$; $//$ Ryout

RegEnable $=4\text{'}$b$1001$; $//$ Gin

addSub $=2\text{'}$b$10$; $//$ xor

end

$4\text{'}$b$0101$: begin $//$ Add$/$Sub$/$Xor last state

triReg $=4\text{'}$b$1001$; $//$ Gout

RegEnable $=$ instruction$[11$:$8]$; $//$ Ryin

end

default: begin

triReg $=4\text{'}$b$0000$;

RegEnable $=4\text{'}$b$0000$;

addSub $=2\text{'}$b$00$;

end

endcase

end

$//$ Assign outputs from the oneHot module results

always @$(*)$ begin

Rin $=$ triStateWires;

Rout $=$ enableWires;

end

endmodule

module Control$\_$Circuit $($

input clk$,$

input rst$,$

input $[15$:$0]$ instruction,

output $[10$:$0]$ Rin,

output $[10$:$0]$ Rout,

output $[1$:$0]$ addSub

$)$;

wire $[3$:$0]$ current$\_$state;

wire $[3$:$0]$ next$\_$state;

reg $[3$:$0]$ state$\_$reg;

$//$ Instantiate Next$\_$State FSM

Next$\_$State fsm $($

$.$instruction$($instruction$),$

$.$current$\_$state$($current$\_$state$),$

$.$next$\_$state$($next$\_$state$)$

$)$;

outputter asd $($

$.$state$($current$\_$state$),$

$.$instruction$($instruction$),$

$.$Rin$($Rin$),$

$.$Rout$($Rout$),$

$.$addSub$($addSub$)$

$)$;

$//$ Register to hold the current state

always @$($posedge clk or posedge rst$)$ begin

if $($rst$)$

state$\_$reg $<=4\text{'}$b$0000$; $//$ Initial state

else

state$\_$reg $<=$ next$\_$state;

end

assign current$\_$state $=$ state$\_$reg;

endmodule

module tristatebuffer $($

input $[15$:$0]$ a$,$

output reg $[15$:$0]$ b$,$

input enable

$)$;

always @$(*)$

begin

if $($enable$)$

b $=$ a;

else

b $=16\text{'}$bZ; $//$ tri$-$state

end

endmodule

module oneHot$($select$,$ out$)$;

input $[3$:$0]$ select;

output reg $[10$:$0]$ out;

always @$($select$)$ begin

out $=11\text{'}$b$00000000000$; $//$ Default value to avoid latches

case $($select$)$

$4\text{'}$b$0000$ : out $=11\text{'}$b$00000000001$;

$4\text{'}$b$0001$ : out $=11\text{'}$b$00000000010$;

$4\text{'}$b$0010$ : out $=11\text{'}$b$00000000100$;

$4\text{'}$b$0011$ : out $=11\text{'}$b$00000001000$;

$4\text{'}$b$0100$ : out $=11\text{'}$b$00000010000$;

$4\text{'}$b$0101$ : out $=11\text{'}$b$00000100000$;

$4\text{'}$b$0110$ : out $=11\text{'}$b$00001000000$;

$4\text{'}$b$0111$ : out $=11\text{'}$b$00010000000$;

$4\text{'}$b$1000$ : out $=11\text{'}$b$00100000000$;

$4\text{'}$b$1001$ : out $=11\text{'}$b$01000000000$;

$4\text{'}$b$1010$ : out $=11\text{'}$b$10000000000$;

endcase

end

endmodule

module Next$\_$State $($

input $[15$:$0]$ instruction,

input $[3$:$0]$ current$\_$state,

output reg $[3$:$0]$ next$\_$state

$)$;

always @$(*)$ begin

case $($current$\_$state$)$

$4\text{'}$b$0000$: begin

case $($instruction$[15$:$12])$

$4\text{'}$b$0000$: next$\_$state $=4\text{'}$b$0001$; $//$ Load

$4\text{'}$b$0001$: next$\_$state $=4\text{'}$b$0010$; $//$ Move

$4\text{'}$b$0010$: next$\_$state $=4\text{'}$b$0011$; $//$ Add$/$Sub$/$Xor $-$ first state

$4\text{'}$b$0011$: next$\_$state $=4\text{'}$b$0011$; $//$ Add$/$Sub$/$Xor $-$ first state

$4\text{'}$b$0100$: next$\_$state $=4\text{'}$b$0011$; $//$ Add$/$Sub$/$Xor $-$ first state

default: next$\_$state $=4\text{'}$b$0000$; $//$ Default state

endcase

end

$4\text{'}$b$0001$: next$\_$state $=4\text{'}$b$0000$; $//$ Return to initial after Load

$4\text{'}$b$0010$: n

$\backslash$table$[[8.,$Msgs$,,,,,,,],[/$tb$\_$processor$/$ck$,1\text{'}$h$1,,\backslash$sqrt$,$L$,,,,],[/$tb$\_$processor$/$rst$,1\text{'}$h$0,,,,,,,],[+/$tb$\_$processor$/$instr$...,16$h$4340,\backslash$sqrt$1010\backslash$sqrt