PLEASE PROVIDE THE VHDL CODE AND BLOCK DIAGRAM!

You have been tasked with designing a Pulse-width-Modulated (PWM) waveform generator. This is to consist of a synthesisable VHDL module to generate a waveform with the following specification: The output from the module is a repetitive waveform with a duty-cycle variable from 0/255 to 255/255 i.e.0% to 100%. This is controlled by an 8-bit std_logic_vector input to the module. The waveform is generated from an input clock of 1kHz. The output waveform frequency is fixed at 1kHz/255. Note that this choice is intended to make the problem easier | Variable Duty-cycle 0-100% T Fixed Period The module is to have the VHDL name pwm_gen and ports exactly as shown in the following figure: width dock roset pwm_gen You may assume inputs are already synchronized to the clock. What is provided to you A very incomplete test-bench that you may extend and use to test your design if you think this useful. This is not to be submitted and is not assessed. I may use a test-bench based on the above to test your design at the following duty-cycles: 0/255, 1/255, 100/255 and 255/255. What is to be submitted What is to be submitted The following items are to be submitted on Canvas. 1. A single plain TEXT document named pwm_gen_XXX.vhd containing the VHDL code for the complete module as described above i.e.entity + architecture with names as stated. (XXX = student ID) If you fail to do this will be unable to test your design and you will receive zero marks. It is expected that VHDL will be internally documented, use sensible symbol names and be correctly indented without unintended line-wraps. 2. A video description of your design explaining how it functions. This video should confirm your understanding of the design. At the very least it should include a walk-through of the above VHDL code. You may find it useful to use additional material such as a block diagram to assist in your explanation. This presentation must be no longer than 5 minutes in duration. There is no demonstration in this video. Notes This is intended to be a challenging task allowing students to demonstrate a deeper understanding of the Unit material. Simplicity (efficiency) and structure, as well as functionality, will be considered in the assessment process. Only general questions will be answered, for example clarification of the task requirements. These must be submitted to the discussion board on Canvas within the first 4-hours of availability of this exercise. I reserve the right to not answer or delete any questions Ideem unsuitable. You must NOT answer other student's questions. You must NOT post material that would lead to cheating. You have been tasked with designing a Pulse-width-Modulated (PWM) waveform generator. This is to consist of a synthesisable VHDL module to generate a waveform with the following specification: The output from the module is a repetitive waveform with a duty-cycle variable from 0/255 to 255/255 i.e.0% to 100%. This is controlled by an 8-bit std_logic_vector input to the module. The waveform is generated from an input clock of 1kHz. The output waveform frequency is fixed at 1kHz/255. Note that this choice is intended to make the problem easier | Variable Duty-cycle 0-100% T Fixed Period The module is to have the VHDL name pwm_gen and ports exactly as shown in the following figure: width dock roset pwm_gen You may assume inputs are already synchronized to the clock. What is provided to you A very incomplete test-bench that you may extend and use to test your design if you think this useful. This is not to be submitted and is not assessed. I may use a test-bench based on the above to test your design at the following duty-cycles: 0/255, 1/255, 100/255 and 255/255. What is to be submitted What is to be submitted The following items are to be submitted on Canvas. 1. A single plain TEXT document named pwm_gen_XXX.vhd containing the VHDL code for the complete module as described above i.e.entity + architecture with names as stated. (XXX = student ID) If you fail to do this will be unable to test your design and you will receive zero marks. It is expected that VHDL will be internally documented, use sensible symbol names and be correctly indented without unintended line-wraps. 2. A video description of your design explaining how it functions. This video should confirm your understanding of the design. At the very least it should include a walk-through of the above VHDL code. You may find it useful to use additional material such as a block diagram to assist in your explanation. This presentation must be no longer than 5 minutes in duration. There is no demonstration in this video. Notes This is intended to be a challenging task allowing students to demonstrate a deeper understanding of the Unit material. Simplicity (efficiency) and structure, as well as functionality, will be considered in the assessment process. Only general questions will be answered, for example clarification of the task requirements. These must be submitted to the discussion board on Canvas within the first 4-hours of availability of this exercise. I reserve the right to not answer or delete any questions Ideem unsuitable. You must NOT answer other student's questions. You must NOT post material that would lead to cheating