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Q3) (25 points) We will form a parity generator for 8-bit data. Check the below Verilog description orm fill in the empty lines. Note, each line requires one statement. module parity_generator_sequential(input_bit,clk,start_bit,parity_type,parity_bit,count); input input_bit,clk,start_bit,parity_type; output reg parity_bit; output reg [3:01 count; reg reg parity_odd=1'bO; reg initial always @ (negedge start_bit) begin count=4'bOOOO; end //this operation will be performed at every clock cycle when the start count bit is set always @ ( begin if (count <4'b1000) begin count parity_even = parity_odd = parity_bit end else begin counte4'bOOOO; end end IS purpose and (5 points) (5 points) (5 points) (5 points) (5 points)