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A Cortex M3 processor is programmed to have 10 interrupts (IRQ 0 to IRQ 9) Please compete the Address Offset column for IRQ2 to IRQ9 While in IRQ 2 handler mode, the processor is reset. Explain what would be the Processor status after reset: IRQ 2 status MSP value (immediately after reset) In Thread Privileged mode, IRQ 3 is requested. While in interrupt handler mode for IRQ 3, IRQ 1 and IRQ 5 happen. Describe the sequence of execution. Assume all the special registers have their reset values