Please show clear and understandable work for both parts. thank you

Determine the circuitry for the overflow detection circuit for a 2's-complement adder subtractor. The inputs are the carry in, Cin, and carry out, Cout, of the most significant full adder. The output should equal 1 when the operation results in an overflow, otherwise the output should equal 0. Determine the SOP min expression for each of the three outputs of a bit-slice of the comparator. A bit-slice of a comparator has five bits of input Gin, Ein, Lin, 1;, and yi. The Gin, Ein and Lin signals are the Gout, Eout, Lout outputs from the comparator in the next, more significant, bit position. The Xi, and y; inputs are the th bits of the N-bit inputs X and Y that are being compared - one bit from each of X and Y is sent to one of the N comparator bit-slices. The bit-slice of a comparator has 3- bits of output, Gout, Eout, Lout. These 3-bits forma l's hot code representing the relative magnitude between X and Y up to that point in the comparision