please sir answer this questions asap i will vote you up

Consider the following code block sw $t1, 4($t2) LW $t3, 4($t2) ADD $t1, $t2, $t1 If you only use Stall and code scheduling to overcome the data hazard in the above code sequence, how many clock cycles are needed? Consider the following duration for each stage, IF= 220 ns ID = 125 ns EX (addition) = 250 ns EX (shift) = 120 ns EX (subtraction) = 220 ns MEM = 150 ns WR - 175 ns WB = 175 ns If we consider the above timing, how many stalls would be needed if we want to overcome the data hazard using Stalls and code scheduling? For executing One lw instruction, how much longer will it take to execute the instruction with 5 stage pipelining compared to single cycle datapath? (only write the value, don't need to mention unit) If we want to execute 395 consecutive sll instructions with 5 stage pipelining what will be the total duration of execution (without any hazards)