Please solve 4.14.3

1w r2,0 (r1) label 1: beq r2.rOlabel2 # not taken once, then taken beq r3.r0,label1 # taken add r1.r3.r1 label2: sw r1,0 (r2) 4.14.1 [10]4.8>Draw the pipeline execution diagram for this code, assuming there are no delay slots and that branches execute in the EX stage. 4.14.2 [10] Repeat 4.14.1, but assume that delay slots are used. In the given code, the instruction that follows the branch is now the delay slot instruction for that branch. 4.14.3 [20] One way to move the branch resolution one stage earlier is to not need an ALU operation in conditional branches. The branch instructions would be "bez rd,1abel" and "bnez rd,1abe"and it would branch if the register has and does not have a zero value, respectively. Change this code to use these branch instructions instead of beq. You can assume that register R8 is available for you to use as a temporary register, and that an seq (set if equal) R-type instruction can be used. 1w r2,0 (r1) label 1: beq r2.rOlabel2 # not taken once, then taken beq r3.r0,label1 # taken add r1.r3.r1 label2: sw r1,0 (r2) 4.14.1 [10]4.8>Draw the pipeline execution diagram for this code, assuming there are no delay slots and that branches execute in the EX stage. 4.14.2 [10] Repeat 4.14.1, but assume that delay slots are used. In the given code, the instruction that follows the branch is now the delay slot instruction for that branch. 4.14.3 [20] One way to move the branch resolution one stage earlier is to not need an ALU operation in conditional branches. The branch instructions would be "bez rd,1abel" and "bnez rd,1abe"and it would branch if the register has and does not have a zero value, respectively. Change this code to use these branch instructions instead of beq. You can assume that register R8 is available for you to use as a temporary register, and that an seq (set if equal) R-type instruction can be used