Please use Xilinx ISE

Design flow :

->Generate truth table

-> simplify the expression (using k-map, etc.) to get the final expression

-> draw gate-level schematic

-> write structural Verilog code for the design

-> write testbench for the design

->simulation using ISIM

-> synthesize and download it to FPGA board

-> test your design using the FPGA board

part 2

Design flow :

-> write behavioral Verilog code for the design

-> write testbench for the design

->simulation using ISIM

-> synthesize and download it to FPGA board

-> test your design using the FPGA board

1. You have been asked to design a full-adder circuit which adds three binary digits xi, y and carry in ci Your circuit should compute the sum out si and carry out ci as shown in Figure 1. You may use any logic gate to design this circuit. Write the Boolean equation for this circuit and give the corresponding gate level schematic diagram for your circuit. Draw this in your laboratory notebook. Implement the circuit in structural Verilog and simulate t in ISIM. Remember to use a test bench and top level circuit. After proving that your unit under test is properly designed, synthesize the circui in the Xilinx environment. Use the appropriate switches and LEDs to prove that your circuit works properly to the TA or instructor 1) show code and simulation results; 2) show board test results Addition of binary digits 0 0 101 0 1 0 0 1 1 0 0 0 1 1 0 1 1 1 1 0 1 0 Fig. 1. Full adder truth table 2. Now create full-adder circuit again using a behavioral Verilog. Again simulate the circuit and implement it on the FPGAboards 1) show code and simulation results; 2) show board test results