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Please write down each step in detail Assume the following The memory is byte addressable Memory accesses are to 1-byte words (not to 4-byte words)

Please write down each step in detail

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Assume the following The memory is byte addressable Memory accesses are to 1-byte words (not to 4-byte words) Virtual addresses are 14 bits wide Physical addresses are 13 bits wide The page size is 512 bytes The TLB is 4-way associative tlb (E-4) with 2 sets (S-2) and a total of 8 entries The TLB and a portion of the page table contents are as shown below TLB Page Table VPN PPNI PN PPN 0x01 0x0 Y OxOd Oxd Y 0x02 0x5 Y l[0x11 0x1 Y 0x03 0x8 Y 0x13 0xf Y 0x04 0xb Y 0x16 0x6 Y Set # Way #0 Way #1 Way #2 Way #3 PPN-0x5 PPN 0xb PPN-0x6 PPN-0x7 PPN 0x3PPN-0x2 PPN-0xa 0x090x19 0x3 Y OxOal 0x1dl0x2Y OxOc0x1f Oxa Y Assume that memory address 0x5bb has been referenced by a load instruction. Determine the virtual page number (VPN) and use that to compute the TLB index and tag that would be used to check the TLB for the translation entry Indicate if the entry is in the TLB (Y/N) Indicate if the memory reference has a valid entry in the page table whether it hits in the TLB or not. Use the information from the page table to translate the VPN to a physical page number (PPN) and then the valid physical address (PA) For values that need a hexidecimal value, do not enter leading zeros even if leading zeros are shown in the value(s) above. For entries that can not be determined (e.g. the PPN or PA if a translation doesn't exist), enter "". Assume the following The memory is byte addressable Memory accesses are to 1-byte words (not to 4-byte words) Virtual addresses are 14 bits wide Physical addresses are 13 bits wide The page size is 512 bytes The TLB is 4-way associative tlb (E-4) with 2 sets (S-2) and a total of 8 entries The TLB and a portion of the page table contents are as shown below TLB Page Table VPN PPNI PN PPN 0x01 0x0 Y OxOd Oxd Y 0x02 0x5 Y l[0x11 0x1 Y 0x03 0x8 Y 0x13 0xf Y 0x04 0xb Y 0x16 0x6 Y Set # Way #0 Way #1 Way #2 Way #3 PPN-0x5 PPN 0xb PPN-0x6 PPN-0x7 PPN 0x3PPN-0x2 PPN-0xa 0x090x19 0x3 Y OxOal 0x1dl0x2Y OxOc0x1f Oxa Y Assume that memory address 0x5bb has been referenced by a load instruction. Determine the virtual page number (VPN) and use that to compute the TLB index and tag that would be used to check the TLB for the translation entry Indicate if the entry is in the TLB (Y/N) Indicate if the memory reference has a valid entry in the page table whether it hits in the TLB or not. Use the information from the page table to translate the VPN to a physical page number (PPN) and then the valid physical address (PA) For values that need a hexidecimal value, do not enter leading zeros even if leading zeros are shown in the value(s) above. For entries that can not be determined (e.g. the PPN or PA if a translation doesn't exist), enter

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