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configurations of the cache to simulate, such as: size, associativity and replacement policy. When you run you simulator, you need to additionally provide the path of the trace file that includes the memory accesses. Your simulator will parse the trace file, which looks like: R 02356257 W 0257777 Each line consists of two parts, the operation type (read or write) and byte address in hexadecimal. After reading each line, the simulator will simulate the impact of that access on the cache state, e.g., the LRU state of the accessed set and the current valid blocks in the set. Your simulator needs to maintain information such as hits, misses and other useful statistics throughout the whole run. In this project, you need to implement two different cache replacement policies: LRU and FIFO. In LRU, the least-recently-used element gets evicted, whereas in FIFO, the element that was inserted the earliest gets evicted. Implementation hint: allocate your cache as a 2D array, where each row is a set. On each item of the array keep track of information like the tag of the data in this block. You can create multiple instances of such a 2D array for different purposes; for example, you can create another 2D array to track the LRU position of the corresponding block in the LRU stack of the set. Assume 64B block size for all configurations Inputs to Simulator The name of your executable should be SIM, and your simulator should take inputs as following: ./SIM is the size of the simulated cache in bytes is the associativity replacement policy: 0 means LRU, 1 means FIFO Write-back policy: 0 means write-through, 1 means write-back trace file name with full path Example: ./SIM 32768811 /home/TRACES/MCF.t This will simulate a 32KB write-back cache with 8-way associativity and FIFO replacement policy. The memory trace will be read from /home/TRACES/MCF.t Note: the trace file will contain addresses that can be for 64-bit system, so you might need data types that are large enough to read them correctly and bookkeep the metadata in your simulator. For example, if the tag is 9 bytes and you allocate your tag array bookkeeping array as an array of integers, you will not be able to store the whole 9 bytes; integer is only 4 bytes. Accordingly, use data types such as long long int and its equivalents in other languages. Output from Simulator: The following outputs are expected from your simulator: a. The total miss ratio for L1 cache b. The \# writes to memory c. The \# reads from memory Use the MiniFE and XSBench provided traces to analyze how the miss ratio of these workloads changes with cache size. Fix cache associativity at 4 , write-back, replacement policy to be LRU, and vary the cache size from 8KB to 128KB in multiples of 2, i.e., 8KB,16KB128KB