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T-Mobile LTE ??11:10 1 12% a bbhosted.cuny.edu Data Path Cycles: Use the following data to answer the questions below: Instruction Memory: Data Memory: ALU and adders Register File Assume that mux, control unit, PC accesses, sign extension unit and wires have no latency [12] 150 ps 250 ps 100 ps 50 ps 1. Using the datapath diagram given for Part 2, determine the time that each of the types of instructions would roquire BEQ JUMP 2. If every instruction esecutes in 1 clock cycle of a fixed length, what is the length of one clock cyck? 3. If every instruction esecutes in 1 clock cycle using a variable length clock with an instruction mix of 15% loads, 25% stores, 45% ALU type, 11% branches and 4% jumps, what is the average length clock cycle? Load cyele time, which allows us to use a pipelined design how many stages are Store BEO JUMP 4. If the datagath is evaleated by leting cach stage of execution determine the used by each type of instraction S. In eeder to use a pipelined design for the datapath, what would be the length of a cyele (in ps)? 6 Using a pipelined design and the above mix of instructions, where a jump always causes a 1 cycle delay, 30% of the load instructions are immediately followed by an instnaction that uses the result (causing a 1-cyle delay), and6 15% of the branch instructions are misdirected (causing a 2-cycle delay). What is the average effective number of cyeles once the pipeline is loaded