Positive$-$edge triggered D flip$-$flop is to be designed using NAND gate based SR latch and NAND gates. Output Q follows input D when input C changes from logic $0$ to logic $1.$ In all other cases the output does not change. Complete the following steps in the design.$($a$)$ State table $($Complete the comment part and write whole table.$)$

$4$ Marks$$State

Inputs Output DCQ

Comments$$a $1$

b $1$

c $0$

d $1$

e $0$

f $0$

g $0$

h $1$

$0011000101111010$

after state after state after state after state after state after state after state after state$($b$)$ Draw the primitive flow table.

$($c$)$ Draw implication table in order to find compatible pairs of states. List compatible pairs.

$($d$)$ Draw merger diagram. Specify the maximal compatibles, minimal set of maximal compatibles that

satisfy closed cover condition. Draw the reduced flow table.

$($e$)$ Draw the transition diagram. Specify the state assignment. Draw the transition table.

$($f$)$ Find equations for S and R so as to implement it with NAND gate based SR latch.

$($g$)$ Show the output assignment properly so as to avoid momentary transition pulses in the output. Find

output equation.