Prelab: Complete a truth table for the expected output of each segment of the common cathode 7-segment display, so that given a four-bit binary input, the display shows the proper digit below for the hexadecimal numbers 0-F. Segment names on a seven segment display 8 Segment layout for 0 - F on a seven segment display Use Karnaugh maps to design minimal circuit realizations for segments a and e, and also complete Karnaugh maps for all segments. You may use any standard TTL chips available in the lab for your designs. In addition to your Karnaugh maps and a detailed schematic for each of the two circuits (including labeled chip and pin numbers) for segments a and e, calculate the expected delay of each of the two circuits, and give a detailed plan for testing the delay time of the segments you will be building in lab. This plan should be of sufficient detail that another student could use your plan for measuring delay and know exactly what to do (how to set inputs, what equipment to use, etc.)