PRELAB ONLY

Lab #6 Flip-Flops Purpose: The goal of this lab is to design two latches and a flip-flop using combination logic gates. Procedure: 1 Construct an SR latch with an enable using a single 74LS00, and connect its three inputs S, R and C to three switches and its two outputs Q and Q to two logic monitors so that you may verify its operation. (a) Obtain a truth table of the circuit. (b) Set both the S and R inputs of the latch to logic 0 and the C input to logic 1. (c) Change the C input to logic 0 while observing the outputs. Discuss your findings. 2 Construct a D latch by modifying the SR latch you built in experiment 1. This latch should have two inputs, D and C (enable), and two outputs Q and Q. (a) Connect D and C to two switches and Q and Q to two logic monitors, so you may verify its operation. (b) Obtain a truth table of the circuit. (c) Discuss the differences between this latch and the SR latch. 3 Construct a master-slave JK flip-flop with two 74LS00 and one 74LS10. (a) Connect the J and K inputs to switches and the CLK input to a pulser. (b) Connect the outputs of the master latch to two logic monitors and the outputs of the slave latch to another two logic monitors, so you may observe the latchs operation. (c) Set both the J and K inputs to one then press and hold the pulser always observing the outputs. (d) Release the pulser and again observe the outputs. (e) Repeat the procedure a few times then discuss the transfer sequence from the input to the output of the master, then from the output of the master to the output of the slave. (f) Verify the flip-flops operation and obtain a truth table for it. (g) Discuss the differences between the D latch and the JK flip-flop, specially, with regards to when the outputs of these devices are allowed to change.

Prelab: Design the above sequential logic circuits and draw the logic diagrams with truth tables for the designed sequential logic circuits.