pridgeport.edupesu/PEGS12 SU SSI JUMLULU.JU 1/1 20.pdf Problem #1: Complete the design of the 2-bit fast adder presented in the class. Minimize the K-maps for the three outputs and draw the logit circuit. Problem #2: Implement the 4-bit Ripple Carry Adder as a sequence of 1-bit Full adders and analyze the delays assuming each gate has a delay of A. Show the hardware design of 1-bit adder, and a block diagram for the 4-bit blocks of the adder indicating how blocks connects to each other