PROBLEM 1 (10 PTS) Leading Zero Detector: This iterative circuit processes a 15-bit input (MSB first) and generates the number of leading O's. before the first 1. Example: If the sequence is: 0000 0000 0111 010 R = 9 If the sequence is: 0001 0001 0011 010 R = 3 The figure depicts the (in ASM form) and a datapath circuit. Note: Counters. If E=sclr=1, Q=0. Input data: x (entered sequentially, MSB first). Output data: R. Complete the timing diagram of the digital circuit where one sequence is evaluated. resetn=0 x S1 47 R LEADING-O start ER + 1, scirR+ 1 DETECTOR done EQ + 1, scrQ1 Z eb 1, db 0 0 0 done z start 1 S2 i 4 EQ sclrg E sdr Q o QER scrR Q E scir start FSM eb db 0 1 b Z counter O to 15 ZE 1 eb 1 db + 1 counter 0 to 15 1 0 0 resetn EQ scrQ db ER eb SCIR b bQ E ER 1 clock EQ + 1 no yes Q=14 EQ1 S3 done 1 EQ + 1, scirQ1 ER 1, scrR+1 0 1 start clock resetn start Xg X7 X6 X5 X4 X3 X2 X1 X14 X13 X 12 X11 X10 o o o o 1 Xg 1 X 1 X 0 X1 X 1 X 0 X1 X 0 X1 X0 X X 0 R b Z state done PROBLEM 1 (10 PTS) Leading Zero Detector: This iterative circuit processes a 15-bit input (MSB first) and generates the number of leading O's. before the first 1. Example: If the sequence is: 0000 0000 0111 010 R = 9 If the sequence is: 0001 0001 0011 010 R = 3 The figure depicts the (in ASM form) and a datapath circuit. Note: Counters. If E=sclr=1, Q=0. Input data: x (entered sequentially, MSB first). Output data: R. Complete the timing diagram of the digital circuit where one sequence is evaluated. resetn=0 x S1 47 R LEADING-O start ER + 1, scirR+ 1 DETECTOR done EQ + 1, scrQ1 Z eb 1, db 0 0 0 done z start 1 S2 i 4 EQ sclrg E sdr Q o QER scrR Q E scir start FSM eb db 0 1 b Z counter O to 15 ZE 1 eb 1 db + 1 counter 0 to 15 1 0 0 resetn EQ scrQ db ER eb SCIR b bQ E ER 1 clock EQ + 1 no yes Q=14 EQ1 S3 done 1 EQ + 1, scirQ1 ER 1, scrR+1 0 1 start clock resetn start Xg X7 X6 X5 X4 X3 X2 X1 X14 X13 X 12 X11 X10 o o o o 1 Xg 1 X 1 X 0 X1 X 1 X 0 X1 X 0 X1 X0 X X 0 R b Z state done