PROBLEM 1 (10 PTS) Leading Zero Detector: This iterative circuit processes a 15-bit input (MSB first) and generates the number of leading O's. before the first 1. Example: If the sequence is: 0000 0000 0111 010 R = 9 If the sequence is: 0001 0001 0011 010 R = 3 The figure depicts the (in ASM form) and a datapath circuit. Note: Counters. If Ersclr=1, Q=0. Input data: x (entered sequentially, MSB first). Output data: R. Complete the timing diagram of the digital circuit where one sequence is evaluated. resetno .R LEADING-O start- - ER DETECTOR done 1. scrR1 S1 1 EQ. 1. sciro eb-1, db0 0 done 2 Start EQE Q 4, EREJ scrosor die FSM start sch 28 counter O to 15 db-DL counter O to 15 resetn clock - 11 bQIS no 0-14 Yes - EQ-1 done 1 EQ1, sciro1 ER + 1, scirr. 1 22222222222222222 resetn ata *14 *13 X12 IX 0 X11 X 0 X X10 XgXgX, * Xs X X X X 00001 1XOX1X1 X1 X state done PROBLEM 1 (10 PTS) Leading Zero Detector: This iterative circuit processes a 15-bit input (MSB first) and generates the number of leading O's. before the first 1. Example: If the sequence is: 0000 0000 0111 010 R = 9 If the sequence is: 0001 0001 0011 010 R = 3 The figure depicts the (in ASM form) and a datapath circuit. Note: Counters. If Ersclr=1, Q=0. Input data: x (entered sequentially, MSB first). Output data: R. Complete the timing diagram of the digital circuit where one sequence is evaluated. resetno .R LEADING-O start- - ER DETECTOR done 1. scrR1 S1 1 EQ. 1. sciro eb-1, db0 0 done 2 Start EQE Q 4, EREJ scrosor die FSM start sch 28 counter O to 15 db-DL counter O to 15 resetn clock - 11 bQIS no 0-14 Yes - EQ-1 done 1 EQ1, sciro1 ER + 1, scirr. 1 22222222222222222 resetn ata *14 *13 X12 IX 0 X11 X 0 X X10 XgXgX, * Xs X X X X 00001 1XOX1X1 X1 X state done