Problem 1: A hypothetical accumulator processor uses one of the following 16- instruction formals, depending on the instruction 4-bit op-code Not-used 4-bit op-code 4-bit register id Not-used 4-bit op-code 1 2-bit address and has the following instruction repertoire Register instructions SET: CLR: DEC: CHP ADD registers IOR register AND registers LDR register STR register: AC - OXFFFF: AC - Ox0000; AC AC + 1: AC - AC - 1: AC -AC; AC-AC register AC-AC register MC - MC & register MC-register register AC; 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Branch Instructions: JMP address: JNA address: JPZ address: HLTE PC address: sf (AC