Problem 1: SRAM memory cell In a SRAM cell shown in Fig. 1, assume all the transistors (M1 - M6) have the same unknown length (L), and M5, M6 have the width WM5 = WM6= lum. Both BL and /BL are precharged to Vpd. Assume the on resistance (Ron) of a PMOS and a NMOS of the same width and length, are identical, Vth, NMos = |Vth,PMOS = 0.4(V) and Vpp=1(V). WL VOD M2 M4 M5 Q M6 M1 M3 BL BL I Figure 1. A SRAM cell a) If Q = 1 and /Q =0 is currently stored in the SRAM cell, and we would like to read the data so that BL=1 and /BL=0 when WL is applied with H, what should be the requirement (width) of M1 and M3? Why? Problem 1: SRAM memory cell In a SRAM cell shown in Fig. 1, assume all the transistors (M1 - M6) have the same unknown length (L), and M5, M6 have the width WM5 = WM6= lum. Both BL and /BL are precharged to Vpd. Assume the on resistance (Ron) of a PMOS and a NMOS of the same width and length, are identical, Vth, NMos = |Vth,PMOS = 0.4(V) and Vpp=1(V). WL VOD M2 M4 M5 Q M6 M1 M3 BL BL I Figure 1. A SRAM cell a) If Q = 1 and /Q =0 is currently stored in the SRAM cell, and we would like to read the data so that BL=1 and /BL=0 when WL is applied with H, what should be the requirement (width) of M1 and M3? Why