Problem 2: A synchronous sequential circuit has one input and one output. If the input sequence 0101 or 0110 occurs, an output of two successive is will occur. The first of these is should occur concident with the last input of the 0101 or 0110 sequence. The circuit should reset when the second 1 output occurs. For example, mput sequence: X = 010011101010 101101 output sequence: Z = 000000000011 000011 a) Derive a Mealy state graph and table with a mmimum number of states (six states). b) Try to choose a good state assignment. Realize the circuit using J-K flip-flops and NAND gates. Repeat using NOR gates. c) Check your answer to (b) using the Logic Aid program. Also use the program to nd the NAND sohition for two other state assignments