Problem 2(a) Carry Look-Ahead Adders and Critical Paths 20pts The internal circuit diagram for a 3-bit Carry-Look-Ahead (CLA) adder is shown in Figure 2(a) below. The critical path or worst-case delay is the longest path from any input to any output. It is used to determine how fast the adder can run. (a) Why would you use a Carry Look Ahead adder instead of a Ripple Carry Adder? [5pts.] (b) Identify the critical path in the diagram. Draw the path in thick lines. [5pts.] (c) Calculate the critical path or worst case delay for this 3-bit CLA Adder assuming each AND/OR gate has a delay of 10ns and each XOR gate has a delay of 25ns. [5pts.] (d) What would be the critical path or worst case delay for a 8-bit CLA Adder assuming the same delays as in part (c)? [5pts.] Pz Po 5 81 So Figure 2(a): A 3-bit Carry-Look-Ahead Adder Problem 2(a) Carry Look-Ahead Adders and Critical Paths 20pts The internal circuit diagram for a 3-bit Carry-Look-Ahead (CLA) adder is shown in Figure 2(a) below. The critical path or worst-case delay is the longest path from any input to any output. It is used to determine how fast the adder can run. (a) Why would you use a Carry Look Ahead adder instead of a Ripple Carry Adder? [5pts.] (b) Identify the critical path in the diagram. Draw the path in thick lines. [5pts.] (c) Calculate the critical path or worst case delay for this 3-bit CLA Adder assuming each AND/OR gate has a delay of 10ns and each XOR gate has a delay of 25ns. [5pts.] (d) What would be the critical path or worst case delay for a 8-bit CLA Adder assuming the same delays as in part (c)? [5pts.] Pz Po 5 81 So Figure 2(a): A 3-bit Carry-Look-Ahead Adder