Problem 3: (6 pts: 2 pts + 4pts) Linux area Problem

Part a) (2 pts) In the Polled I/O, why did we need to modify the Nave Receive (RX) to Polled Receive but it would be ok to leave the Transmit (TX) execute a while loop?

Part b) (4 pts) A fictitious processor (CPU) has a fictitious OS loaded and together they have the following characteristics/performance metrics:

Load from memory: 300 clock cycles; store to memory: 250 clock cycles; interrupt latency for first interrupt (initiating): 3,000 instructions (assume each instruction takes two clock cycles); interrupt latency for second interrupt (concluding): 50 instructions (also assume each instruction takes two clock cycles); set up information for DMA: 4 loads (base and bound registers).

Give an example in the packet size that may be transferred (numerical) in which PIO has a shorter latency than DMA. Remember that in PIO, each data byte is transmitted separately.

Next, assume that we are allowed to transmit or receive more than one byte at a time, as many as the capacity of a memory mapped register. First, assuming we have a RISC-V processor, how many bytes of data from memory can be stored in such a register? (Hint: RISC-V architecture is 64-bit.) Now, based on these updated assumptions, can you determine again for what packet sizes PIO has a shorter latency than DMA?

please give full steps, thank you! I will give upvote..