Problem #4 (a) Briefly explain the sources of interrupts and in which stage they can occur in MIPS pipelined processor. (b) What are the differences between vectored and non-vectored interrupts? Which approach is supported by MIPS processor? Explain (providing critical details) how interrupts (exceptions) are handled by MIPS pipelined processor and what kind of modifications are done in the data path to support interrupts in MIPS. (c) What are the differences between NOP, stall and flush? Why do we need such operations in a pipelined processor? Give an explicit example for the use of each type of such operations. (d) What is a branch delay slot? Give an example of its use. Why this technique is not popular in deep pipelined systems? Be specific in your response.