Problem #4 (Pipelining) Assume that individual stages of the data path have the following latencies: IF 5ns 10ns 10ns 10ns 5ns ID EX MEM WB (a) What is the clock cycle time in a pipelined and a single cycle non-pipelined processor? (b) What is the latency of an instruction in a pipelined and a single cycle non-pipelined processor? (c) What are the speed-up that could be achieved with the pipelined processor over the non- pipelined processor for two programs containing 10 instructions and 10000 instructions, respectively