Problem 418 points: You have a 2-way set associative L1 cache that is 8KB, with 4-word cache lines. You get the following sequence of writes to the cache -- each is a 32-bit address in hexadecimal 0x1000 0x1004 0x1010 0x11c0 0x2000 0x21c0 0x3400 0x3404 0x3f00 0x2004 0x1004 a) [4 points] How many cache misses occur with an FIFO policy? b) [4 points] Would the miss-rate increase or decrease if the cache was the same size, but direct-mapped? Explain. 9