Problem #5 (Pipeline Hazards) Given the following sequence of assembly language instructions, indicate all data dependencies (RAW, WAR, WAW) that exist between instructions. Insert nops to ensure correct execution of the code for a 5-stage pipeline system. Assume that the first half of the clock cycle write- back stage writes to register file and the second half of the clock cycle the decode stage performs a read of source registers I1: lw $4, 8($16) 12: lw S5, 16($4) 13: add $2, $4, $5