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Problem 7: (9 pts) Part 1: (6 pts) Translate function f into RISC-V assembly language. Assume that the function declaration for function g is: int

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Problem 7: (9 pts) Part 1: (6 pts) Translate function f into RISC-V assembly language. Assume that the function declaration for function g is: int g (int a, int b); The code for function f is as follows: int f (int a, int b, int c, int d) return g(g(a,b), c+d): Part 2: (3 pts) Can we determine the contents of registers: x10-x14, x8, x1, and sp? We know what the entire function f looks like, but for function g we only know its declaration. Solution: Problem 8: (11 pts) Part 1: (3 pts) Consider the following code 1b x5, 0 (x10) sd x5, 8 (x10) Assume that register x10 contains address 0x10000000 and the data at address is 0x7FEEDDCCBBAA9987 Q1: What value is stored in 0x10000008 on a big-endian machine? Q 2: What value is stored in 0x10000008 on a little-endian machine? Part 2: (5 pts) Write the RISC-V assembly code that creates the above 64-bit constant and stores that value to register x11 Part 3: (3 pts) Provide the instruction type, assembly language instruction, and binary representation of instruction described by the following RISC-V fields: opcode 0x3, funct3-0x3, rs1-27, rd-3, imm 0x4 Problem 7: (9 pts) Part 1: (6 pts) Translate function f into RISC-V assembly language. Assume that the function declaration for function g is: int g (int a, int b); The code for function f is as follows: int f (int a, int b, int c, int d) return g(g(a,b), c+d): Part 2: (3 pts) Can we determine the contents of registers: x10-x14, x8, x1, and sp? We know what the entire function f looks like, but for function g we only know its declaration. Solution: Problem 8: (11 pts) Part 1: (3 pts) Consider the following code 1b x5, 0 (x10) sd x5, 8 (x10) Assume that register x10 contains address 0x10000000 and the data at address is 0x7FEEDDCCBBAA9987 Q1: What value is stored in 0x10000008 on a big-endian machine? Q 2: What value is stored in 0x10000008 on a little-endian machine? Part 2: (5 pts) Write the RISC-V assembly code that creates the above 64-bit constant and stores that value to register x11 Part 3: (3 pts) Provide the instruction type, assembly language instruction, and binary representation of instruction described by the following RISC-V fields: opcode 0x3, funct3-0x3, rs1-27, rd-3, imm 0x4

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