Problem D. On an ARMv7-M or ARMv8-M processor, assuming that [R1] = 0x010E0C2D, [R2] = 0xFDB97531, [R3] = 0x0000000C, [N-bit] = 1, [Z-bit] = 0, [C-bit] = 0, [V-bit] = 1, predict the 32-bit [R1], [N-bit], [Z-bit), and [C-bit) after an ARM instruction is executed in EACH case. (These instructions are NOT executed one after the other; instead, each instruction starts with the initial conditions given in the statement.) (a) MOVS R1, #0xFAB (b) MVNS R1, #0x2FC (c) MVNS R1, R2, LSL R3 (d) LSRS R1, R2, R3 (e) MVNS R1, R2