Problem: Write a Verilog code that starts at $0$ and increments to $9$ on a seven segment PMOD display that uses both PMODA and PMODB on the PYNQ$-$Z$2$ FPGA development board. $($Zynq$7020)$

I have been struggling to get the counter to work. I have successfully got each number to display on the seven segment, but I can not get a loop to work. I have added buttons and switches, but they do not make the problem better. Does someone have an idea as to where I can improve my code?

Constraint file:

set$\_$property ALLOW$\_$COMBINATORIAL$\_$LOOPS TRUE $[$get$\_$nets clk$]$

## Clock signal $125$ MHz

set$\_$property $-$dict $\{$ PACKAGE$\_$PIN H$16$ IOSTANDARD LVCMOS$33\}[$get$\_$ports $\{$sysclk $\}]$; #IO$\_$L$13$P$\_$T$2\_$MRCC$\_35$ SCh$=$SYSCIk

create$\_$clock $-$add $-$name sys$\_$clk$\_$pin $-$period $8\mathrm{.}00[$get$\_$ports $\{$sysclk $\}]$;

## PmodA

set$\_$property $-$dict $\{$ PACKAGE$\_$PIN Y$18$ IOSTANDARD LVCMOS$33\}[$get$\_$ports $\{$PMODA$[0]\}]$; # IO$\_$II$7$P$\_$T$2\_34$ SCh$=$ja$\_$p$[1]$

set$\_$property $-$dict $\{$ PACKAGE$\_$PIN Y$19$ IOSTANDARD LVCMOS$33\}[$get$\_$ports $\{$PMODA$[1]\}]$; #IO$\_$L$17$N$\_$T$2\_34$ SCh$=$ja$\_$n$[1]$

set$\_$property $-$dict $\{$ PACKAGE$\_$PIN Y$16$ IOSTANDARD LVCMOS$33\}[$get$\_$ports $\{$PMODA$[2]\}]$; # IO$\_$I$7$P$\_$TI$\_34$ SCh$=$ja$\_$p$[2]$

set$\_$property $-$dict $\{$ PACKAGE$\_$PIN Y$17$ IOSTANDARD LVCMOS$33\}[$get$\_$ports $\{$ PMODA$[3]\}]$; # IO$\_$L$7$N$\_$TI$\_34$ SCh$=$ja$\_$n$[2]$

## PmodB

set$\_$property $-$dict $\{$ PACKAGE$\_$PIN W$14$ IOSTANDARD LVCMOS$33\}[$get$\_$ports $\{$ PMODB$[0]\}]$; # IO$\_$L$8$P$\_$T$1\_34$ SCh$=$jb$\_$p$[1]$

set$\_$property $-$dict $\{$ PACKAGE$\_$PIN Y$14$ IOSTANDARD LVCMOS$33\}[$get$\_$ports $\{$PMODB$[1]\}]$; # IO$\_$L$8$N$\_$T$1\_34$ SCh$=$jb$\_$n$[1]$

set$\_$property $-$dict $\{$ PACKAGE$\_$PIN T$11$ IOSTANDARD LVCMOS$33\}[$get$\_$ports $\{$ PMODB$[2]\}]$; # IO$\_$LIP$\_$TO$\_34$ SCh$=$jb$\_$p$[2]$

set$\_$property $-$dict $\{$ PACKAGE$\_$PIN T$10$ IOSTANDARD LVCMOS$33\}[$get$\_$ports $\{$PMODB$[3]\}]$; # IO$\_$IIN$\_$TO$\_34$ SCh$=$jb$\_$n$[2]$

Source Code:

module Seven$\_$Segement$($

output reg $[3$:$0]$ PMODB,

output reg $[3$:$0]$ PMODA

$)$;

reg $[7$:$0]$ seg$\_$values $[0$:$9]$;

reg $[3$:$0]$ counter;

reg clk;

reg $[18$:$0]$ delay$\_$counter;

initial begin

$//$ Initialize clock to $0$

clk $=0$;

seg$\_$values$[0]=8\text{'}$b$11111100$; $//0$

seg$\_$values$[1]=8\text{'}$b$01100000$; $//1$

seg$\_$values$[2]=8\text{'}$b$11011010$; $//2$

seg$\_$values$[3]=8\text{'}$b$11110010$; $//3$

seg$\_$values$[4]=8\text{'}$b$01100110$; $//4$

seg$\_$values$[5]=8\text{'}$b$10110110$; $//5$

seg$\_$values$[6]=8\text{'}$b$10111110$; $//6$

seg$\_$values$[7]=8\text{'}$b$11100000$; $//7$

seg$\_$values$[8]=8\text{'}$b$11111110$; $//8$

seg$\_$values$[9]=8\text{'}$b$11100110$; $//9$

$//$ Set clock frequency to $125$ MHz

#$10$;

$//$ Start the delay counter

delay$\_$counter $=0$;

end

always #$1$ clk $=$ ~clk; $//$ Toggle clock every $1$ time unit

always @$($posedge clk$)$ begin

$//$ Increment the counter

if $($delay$\_$counter $==0)$

counter counter $+1$;

$//$ Reset the counter if it reaches $10$

if $($counter $==10)$

counter ;

$//$ Increment the delay counter

delay$\_$counter delay$\_$counter $+1$;

end

always @$*$ begin

$//$ Assign segment values based on the counter

$\{$PMODA$,$ PMODB$\}=$ seg$\_$values$[$counter$]$;

$//$ Reset the delay counter after $2$ seconds $(125$ MHz clock assumed$)$

if $($delay$\_$counter $==2*125\_000\_000)$

delay$\_$counter ;

end

endmodule

We are using Vivado Software