Problem_#01] The input shown signal shown below is applied to an inverter. Draw a timing diagram showing the input and output. VIN HIGH LOW Problem_#02] A cascaded inverter array is show below. If a logic l" is applied at A, determine the logic level at point B, C, D, E, & F. E F Problem_#03] The input shown signal shown below is applied to the AND gate. Draw a timing diagram showing the input and output. D- Problem_#04] The input shown signal shown below is applied to the AND gate. Draw a timing diagram showing the input and output. A HD B