Problems in this exercise assume that the logic blocks used to implement a processor's datapath have the following latencies:

$\backslash$table$[[\backslash$table$[[$WMat$],[$D$-$ME$]],\backslash$table$[[$Register$],[$Flle$]],,,-,\backslash$table$[[$Sign$],[$extend$]],PC,$Regls$],[250,150ps,25r,200p,150,50p,30r,20ps$