Procedure: Design a 5-bit binary decoder with VHDL as shown in Fig. 1. Fig.1 Block diagram of the 5-bit binary decoder. The design must follow the next approaches: 1. Using the straight VHDL sentences such as conditional statements. Notice that you are using the LEDs in the 7-Segment display independently rather than to show the display pattern. The binary decoder has 32 outputs which are connected directly to the LEDs in the 7 -segment displays. Start using the LEDs in the original order 06 (you will only need LEDR Lo- 3 of HEX5 to complete the 32 LEDs in total needed for this design). - Create a QII project in VHDL. Compile and simulate the project to verify the correct circuit operation. Use conditional statements to build the decoder (i.e. IF, CASE, etc.) - Download the design to the board to verify the correct operation of the circuit. Add a copy of your functional simulation to your project report. Explain why you chose the conditional sentence used and how this decision impact the circuit implementation. Make note of the number of logic units used as per QII report for comparing with part 2 of the lab. Your project report should reflect if the project worked correctly in the board and explain the causes if it did not work. Archive your QII project after it is pracically tested and submit it with your project report. All projects will be run and verified. Use QII LPM_DECODE module in LPM library from Altera to build the same circuit in Fig. 1. - Create a second QII project and instantiate a LPM_DECODE component module. A hierarchical design will result with two levels: a top level VHDL file that host the I/O variables and low level VHDL file that is generated with the IP Catalog wizard. Compile, simulate and verify the operation of the project