Project Description:

Implement the transmitter$/$receiver circuit shown in Figure $1$ using Verilog. The circuit can be implemented using any type of model $($Behavioral$,$ structural etc$)$ and should meet the following requirements:

Figure $1.$ Circuit Diagram

The circuit's functionality: In this circuit, the transmitter reads data from the source memory and sends it to the receiver, which is responsible for storing the data in the receiving memory.

Design Requirements:

The starting address of where to read the data is stored in Source Reg.

The starting address of where to store the data is stored in Dest. Reg.

The copy should stop when it reaches this special data pattern $=FFF{F}_h.$ It should copy it$,$ then stop.