Project description:

In this project, we need to upgrade our accumulator computer described and implemented in the example above to a

bit more complicated computer. The memory in this computer system is $16-$bit cell memory with size of $128$ cells

$($i$.$e$.$ cell width $=16$bits$).$ The memory is synchronous to the CPU, and the CPU can read$/$write one cell in a

single clock cycle. The memory can only be aceessed through the memory address register $($MAR$)$ and the

memory buffer register $($MBR$).$

The CPU has a program counter $($PC$)$ register and an instruction register $($IR$).$ This CPU has eight $16-$bit

general$-$purpose registers $R0-R7.$

The $16-$bit instruction format is as follow:

Addressing Modes bits for the last field of the instruction $(8$bits$)$:

$00=>$ Direct memory address

$01=>$ Register

$10=>$ Register Indirect

$11=>$ Constant

The opcodes are:

O$00$ LOAD Ri$,$ operand: loads register Ri with a memory cell of address operand$/$register content of address operand$/$

memory cell of address in register operand$/$or a constant integer operand.

$001$ STORE Ri$,[$M$]$: Stores the contents of Ri in memory cell of address M$.($only mode$=00$ is supported with store

instruction$)$

$010$ ADD Ri$,$ operand: Adds the contents of Ri to the operand, and store the result in Ri$.$

$011$ SUB Ri$,$ M: subtract the contents operand from Ri and store the result in Ri$.$

$0100$ MUL Ri$,$ M: Multiplies the contents of Ri by the operand, and store the result in Ri$.$

$0101$ DIV Ri$,$ M: Divides the contents of operand by Ri and store the result in Ri$.$

Assume data is singed $16-$bit integers in two's complement format. please write full verilog code