Project title: Design and Implementation of a Simple ALU using Verilog HDL Due date: Tuesday, January $23$rd$,2024$This project is to be done individually$\mathrm{.}1)$ Youneedtosubmityourcodes$\mathrm{.}2)$ Writeareportforyourresultsbyprovidingthecodeandthesimulationresultsofeverycomponent as well as the whole system.NOTE: The grading of the project will be via discussion. This project should be implemented in Verilog HDL using Quartus softwareDO NOT: Give$/$receive code or proofs to$/$from other students DO: Meet with other students to discuss the project $($it is best not to take any notes during such meetings, and to re$-$work project on your own$)$ Use online resources $($e$.$g$.$ Wikipedia$)$ to understand the concepts needed to solve the projectProject Description:In this project, you will design a simple Arithmetic Logic Unit $($ALU$)$ using Verilog Hardware Description Language $($HDL$).$ The ALU should be capable of performing four basic arithmetic and logic operations: addition, subtraction, bitwise AND, and bitwise OR$.$Objective: To develop a comprehensive understanding of Verilog HDL for hardware description. To design and implement a simple ALU with four basic functionalities. To explore structural, dataflow, and behavioral modeling techniques in Verilog. Tasks:$1.$ ALUDesign:o Define inputs and outputs of the ALU. o Select four essential arithmetic and logical operations to implement $($e$.$g$.,$ addition, subtraction, AND, OR$).$o Create a block diagram representing the ALU's structure. $2.$ VerilogModules:o Develop a top$-$level ALU module with appropriate input$/$output ports.o Design separate modules for each of the four chosen operations, utilizinga combination of structural and behavioral modeling approaches. Modules: Adder, Subtractor, AndGate, OrGate, and ALU $($top$-$level module$).$ The ALU design should be modular, comprising separate modulesfor each functionality. Implement the modules using structure, dataflow, and behavioralmodeling as below:$1.$ Utilize structural modeling for Adder, Subtractor, and logicgates$\mathrm{.}2.$ Implement dataflow modeling for connecting the modules$\mathrm{.}3.$ Utilize behavioral modeling for the top$-$level ALU module$\mathrm{.}3.$ Input$/$Output:o The ALU should take two $4-$bit inputs $($A and B$).$o Include a $3-$bit control input $($OpCode$)$ to select the operation: $3\text{'}$b$000$: Addition $3\text{'}$b$001$: Subtraction $3\text{'}$b$010$: Bitwise AND $3\text{'}$b$011$: Bitwise ORo Output the result $($Result$)$ of the selected operation. $4.$ TestingandSimulation:o Test various combinations of input values and control codes to ensure the ALU operates as expected. Apply a variety of input test cases to cover all possible combinations.o Simulate the ALU Components$/$Modules using a Verilog simulator and analyze the resultso Simulate the ALU using a Verilog simulator and analyze the results. $5.$ Documentation:o Provide clear and concise comments within the Verilog code for better understanding.o Prepare a well$-$formatted project report detailing the design process, code implementation, simulation results, and conclusions.Evaluation: Correctness of the ALU's functionality. Efficiency of the Verilog code. Quality of the simulation results. Clarity of documentation and project report.Additional Guidelines: Adhere to Verilog coding conventions and best practices. Consider using a design hierarchy for better organization. Thoroughly test the ALU under various input scenarios. Document any assumptions or design choices made during the project.Submission Requirements:You need to submit the following files as one compressed folder $($e$.$g$.,.$zip, $.$rar$)$ for your project by January, $23$rd$,2024($up to midnight$).$ Then, name your folder as $($hdlProject$\_$LastName$\_$FirstName$\_$StudetnsID.zip$).$ Verilog HDL source code for each module. Verilog code for the ALU and its modules. Simulation files. The simulation results $($waveforms$)$ of every individual component. The schematic files for the whole system $($that shows the structural modeling of the final system design$)$ Comprehensive project report $($in PDF format$),$ including design details, simulation results, and conclusions. The project discussion will be based on the above bullets, as well as$,$ you will be asked to slightly modify the system. This way, we can assess your understanding of the project.