Provide an explanation for why the four outputs in the ALU works correctly.

testbench.sv

module tb_alu();

logic [31:0] a, b; logic [1:0] ALUControl; logic [31:0] Result; logic [3:0] ALUFlags;

alu DUT (a, b, ALUControl, Result, ALUFlags);

initial begin

$monitor("a = %d b = %d ALUControl = %b Result = %d ALUFlags = %b ", a, b, ALUControl, Result, ALUFlags); a = 17; b = 5; ALUControl = 00; #5 a = 3; b = 1; ALUControl = 01;

#5 a = 12; b = 12; ALUControl = 10;

#5 a = 12; b = 15; ALUControl = 11; end

initial #100 $finish; endmodule

design.sv

module alu( input logic [31:0] a, b, input logic [1:0] ALUControl, output logic [31:0] Result, output logic [3:0] ALUFlags);

logic neg, zero, carry, overflow; logic [31:0] condinvb; logic [32:0] sum;

assign condinvb = ALUControl[0] ? ~b : b; assign sum = a + condinvb + ALUControl[0];

always_comb casex (ALUControl[1:0]) 2'b0?: Result = sum; 2'b10: Result = a & b; 2'b11: Result = a | b; endcase

assign neg = Result[31]; assign zero = (Result == 32'b0); assign carry = (ALUControl[1] == 1'b0) & sum[32]; assign overflow = (ALUControl[1] == 1'b0) & ~(a[31] ^ b[31] ^ ALUControl[0]) & (a[31] ^ sum[31]); assign ALUFlags = {neg, zero, carry, overflow};

endmodule

Please provide an explanation why the code prints out this output below.

Output :

a = 17 b = 5 ALUControl = 00 Result = 22 ALUFlags = 0000 a = 3 b = 1 ALUControl = 01 Result = 2 ALUFlags = 0010 a = 12 b = 12 ALUControl = 10 Result = 12 ALUFlags = 0000 a = 12 b = 15 ALUControl = 11 Result = 15 ALUFlags = 0000