Provide the state diagram (in ASM form) and complete the timing diagram of the FSM whose VHDL description is listed below. library ieee; use ieee.std_logic_1164.all; entity myfsm is port (clk, resetn: in std_logic; a, b: in std_logic; x, w, z: out std_logic); end myfsm; architecture behavioral of myfsm is type state is (S1, S2, S3); signal y: state; begin Transitions: process (resetn, clk, a, b) begin if resetn = '0' then y if a = '1' then if b = '1' then y if a = '0' then y if b = '1' then y if a = '0' then z w if b = then x if a = '1' then if b = '1' then y if a = '0' then y if b = '1' then y if a = '0' then z w if b = then x