Pulse Width Modulation is one of the important functions of timer. PWM is a technique to control analogue circuits with digital output from microcontroller. As you all know that an Analogue signal is the one whose value varies continuously with time whereas digital signals can only be either high or low. PWM is used for generating an analogue signal using a digital source. PWM consist of two main components:- 1.) Duty cycle 2.) Frequency Duty cycle describes the amount of time, the signal is in HIGH state as a percentage of total time, it takes to complete one cycle. Frequency describes how fast the PWM completes a cycle and therefore how fast it switches between HIGH and LOW. By cycling a digital signal ON and OFF at a fast enough rate and at a certain duty cycle, the output will appear like a constant voltage analogue signal. For eg: To create a 2V signal from a digital source which is either HIGH(5V) or low (0). We can use PWM with duty cycle of 40% here. This 40% duty cycle would yield an average voltage of 5x0.4=2V. You are two create pwm module which has the inputs start, Arr,Crr ,clock and the outputs done and pwmout. When the start signal is asserted the module starts to count from 0 (up to ARR-1). When the count value reaches to ARR-1 the done signal is set to 1 (it is 0 other wise) and the counter stops. The pwmout is high as long as the count value is less then CRR value , low otherwise. (the duty cycle is determined by the ratio CRR/ARR, the pwm period is determined by the ARR value i periodpwm=ARR* clock speed) Deliverables : Your verilog project with a complete testbench ( trying different duty cycles and ARR values.) Your verilog files in a directory named after your name and surname (in ASCII). Pulse Width Modulation is one of the important functions of timer. PWM is a technique to control analogue circuits with digital output from microcontroller. As you all know that an Analogue signal is the one whose value varies continuously with time whereas digital signals can only be either high or low. PWM is used for generating an analogue signal using a digital source. PWM consist of two main components:- 1.) Duty cycle 2.) Frequency Duty cycle describes the amount of time, the signal is in HIGH state as a percentage of total time, it takes to complete one cycle. Frequency describes how fast the PWM completes a cycle and therefore how fast it switches between HIGH and LOW. By cycling a digital signal ON and OFF at a fast enough rate and at a certain duty cycle, the output will appear like a constant voltage analogue signal. For eg: To create a 2V signal from a digital source which is either HIGH(5V) or low (0). We can use PWM with duty cycle of 40% here. This 40% duty cycle would yield an average voltage of 5x0.4=2V. You are two create pwm module which has the inputs start, Arr,Crr ,clock and the outputs done and pwmout. When the start signal is asserted the module starts to count from 0 (up to ARR-1). When the count value reaches to ARR-1 the done signal is set to 1 (it is 0 other wise) and the counter stops. The pwmout is high as long as the count value is less then CRR value , low otherwise. (the duty cycle is determined by the ratio CRR/ARR, the pwm period is determined by the ARR value i periodpwm=ARR* clock speed) Deliverables : Your verilog project with a complete testbench ( trying different duty cycles and ARR values.) Your verilog files in a directory named after your name and surname (in ASCII)
