Put the sequence of cache interactions in the proper order:

	A. L1 cache checks for an empty block in the set
	B. The L1 cache controller determines the cache set, the requested cache tag and the block offset
	C. L1 cache sends the L2 cache controller a memory address
	D. The L1 cache Controller determines the least recently used block entry
	E. L2 cache circuits determine whether the requested tag is in the set by matching existing cache tags to the tag of the request
	F. L1 cache identifies the byte field in the L1 cache cache block and returns it to The CPU
	G. L2 cache set tag match
	H. L1 cache receives a block from the L2 cache controller
	I. No L1 cache set tag match
	J. No empty block in L1 cache set
	K. The L2 cache controller determines the cache set, the requested cache tag and the block offset
	L. L1 cache writes the block data, LRU info and cache tag to the cache block
	M. The CPU sends the L1 cache controller a memory address
	N. L1 cache circuits determine whether the requested tag is in the set by matching existing cache tags to the tag of the request
	O. L2 cache identifies the byte field in the L2 cache cache block and returns it to L1 cache