Q: (25Marks) For the following VHDL code: 1- Draw the internal design of the circuit (RTL). 2- Draw the z output waveform in relation to the clock if x={10) and y=(5), 3. What specific function does this circuit perform? library IEEE; use IEEE.9TD_LOGIC_1164. ALL; use IEEE. STD LOGIC UNSIGNED. ALL; antity exam is Port ( elk : in stu_logie; sel : in STD_20510_T2CSOs (1 downto 0); x,y: in STD LOGIC VECTOR (7 downto 0); zi cut OTD_LOGIC_VECTOR (7 downto 0)); end exas: Q: (25Marks) For the following VHDL code: 1- Draw the internal design of the circuit (RTL). 2- Draw the z output waveform in relation to the clock if x={10) and y=(5), 3. What specific function does this circuit perform? library IEEE; use IEEE.9TD_LOGIC_1164. ALL; use IEEE. STD LOGIC UNSIGNED. ALL; antity exam is Port ( elk : in stu_logie; sel : in STD_20510_T2CSOs (1 downto 0); x,y: in STD LOGIC VECTOR (7 downto 0); zi cut OTD_LOGIC_VECTOR (7 downto 0)); end exas