Q$5$: Assume a processor with the Base case which has the following instruction classes:

Integer ALU instructions: CPI$=0\mathrm{.}5$ and instruction count$=1$

Load instructions: CPI$=0\mathrm{.}2$ and instruction count$=5$

Store instructions: $\frac{C}{P}$I $=0\mathrm{.}1$ and instruction count$=1$

Branch instructions: $\frac{C}{P}$I $=0\mathrm{.}2$ and instruction count $=2$

$($a$)$ What is the CPU clock cycles for the Base case?

$($b$)$ What is the CPU clock cycles for the case A which increased the instruction count of Integer ALU instructions to $2$ as well as reduced the instruction count for Load instructions to $1?$

$($c$)$ What is the CPU clock cycles for the case B which increased the instruction count of Store instructions to $2$ as well as reduced the instruction count for Branch instructions to $1?$

$($d$)$ Which case will have the best performance $($Base$,$ A$,$ or B$)?$