Q. A system has a 2 GHz clock rate, and an L1 cache with a 1 ns hit time and a 10% miss rate. The hit time for DRAM is 100 ns. Assume that 40% of all instructions being executed access memory.

a) [5 points] What is the Average Memory Access Time (AMAT)?

b) [8 points] Assuming a base CPI of 2.0 without any memory stalls, what is the total CPI?

For the next two parts, we will consider a revision of the design given above, adding an L2 cache with a 4% miss rate and a 10 ns hit time.

c) [5 points] What is the AMAT with the addition of an L2 cache? Is the AMAT better or worse with the L2 cache?

d) [8 points] Assuming a base CPI of 2.0 without any memory stalls, what is the total CPI with the additional of an L2 cache?